The present invention relates in general to vertical field effect transistor (VFETs), and more specifically, to fabrication methodologies and resulting structures for providing different channel orientations for n-type VFETs and p-type VFETs.
A field effect transistor (FET) is a semiconductor device in which output current, i.e., source-drain current, is controlled by the voltage applied to a gate structure of the semiconductor device. An FET has three terminals, namely, a gate structure, a source region and a drain region. As used herein, the term “drain” means a doped region in semiconductor device located at the end of the channel region, in which carriers are flowing out of the transistor through the drain. The term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel region. The channel region is the region underlying the gate structure and between the source and drain of the semiconductor device that becomes conductive when the semiconductor device is turned on.